Methods for decomposing circuit design layouts and for fabricating semiconductor devices using decomposed patterns
US8555215B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2012 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Feb 20, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/70
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.