Automatic verification of dependency
US8555226B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2012 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Sep 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach is provided in which a formal verification tool sends a condition signal to a first circuit instance and to a second circuit instance, which are both instances of an electric circuit design. The formal verification tool selects a common input port and sends a first input value to the common input port of the first circuit instance and sends a second input value, which is different than the first input value, to the common input port of the second circuit instance. In turn, the first circuit instance generates a first output value and the second circuit instance generates a second instance value, which are utilized to verify dependencies between the electronic circuit's input ports and output ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.