Method for forming N-shaped bottom stress liner
US8557668B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2012 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Apr 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.