Exclusive-option chips and methods with all-options-active test mode
US8558566B2 · kind B2 · utility
0Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2011 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Jan 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31924
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.