Vialess integration for dual thin films—thin film resistor and heater
US8558654B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 29, 2011 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Dec 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process is described for integrating two closely spaced thin films without deposition of the films through deep vias. The films may be integrated on a wafer and patterned to form a microscale heat-trimmable resistor. A thin-film heating element may be formed proximal to a thin-film resistive element, and heat generated by the thin-film heater can be used to permanently trim a resistance value of the thin-film resistive element. Deposition of the thin films over steep or abrupt topography is minimized by using a process in which the thin films are deposited in a sequence that falls between depositions of thick metal contacts to the thin films.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.