Data receiver, semiconductor device and memory device including the same
US8559241B2 · kind B2 · utility
2Cited by
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20Claims
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Key dates
| Filing date | May 18, 2011 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Apr 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.