Patent · US Active

Method for producing a power semiconductor arrangement

US8563364B2 · kind B2 · utility

4Cited by

4References

25Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thilo Stolze · Arnsberg, DE
Guido Strotmann · Uchte, DE
Karsten Guth · Soest, DE

Key dates

Filing date	Sep 29, 2011
Grant date	Oct 22, 2013
Priority date	—
Expiry date	Sep 29, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/19107
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In a method for producing a power semiconductor arrangement, a dielectric insulation carrier with a top side and a top metallization layer arranged on the top side are provided. Also provided are a semiconductor chip and at least one electrically conductive contact pin, each pin having a first end and an opposite second end. The semiconductor chip is sintered or diffussion soldered to the top metallization layer. Between the first end and the top metallization layer an electrically conductive connection is formed, in which electrically conductive connection material of the contact pin is in direct physical contact with the material of the top metallization layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.