High voltage-resistant lateral double-diffused transistor based on nanowire device
US8564031B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2011 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Apr 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/83
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The invention provides a high voltage-resistant lateral double-diffused transistor. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.