Method of forming a semiconductor device package
US8569114B2 · kind B2 · utility
1Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2010 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Feb 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a method of forming a semiconductor package. In the method, a first package including a first chip on a first substrate is formed, a second package including a second chip on a second substrate is formed, a molding cap provided with a via hole and a recess structure configured to receive the first chip is formed, and the second package is provided on the first package with the molding cap being therebetween such that the recess receives the first chip. The via hole and the recess structure are simultaneously formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.