Integrated circuit arrays and semiconductor constructions

US8569831B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Lars Heineck · Dresden, DE
• Shyam Surthi · Boise, US
• Jaydip Guha · Boise, US

Key dates

• Filing date: May 27, 2011
• Grant date: Oct 29, 2013
• Expiry date: Nov 16, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/63
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.