Asynchronously scheduling memory access requests
US8572322B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2010 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Jun 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system employs a scheduler to schedule pending memory access requests and a memory controller to service scheduled pending memory access requests. The memory access requests are asynchronously scheduled with respect to the clocking of the memory. The scheduler is operated using a clock signal with a frequency different from the frequency of the clock signal used to operate the memory controller. The clock signal used to clock the scheduler can have a lower frequency than the clock used by a memory controller. As a result, the scheduler is able to consider a greater number of pending memory access requests when selecting the next pending memory access request to be submitted to the memory for servicing and thus the resulting sequence of selected memory access requests is more likely to be optimized for memory access throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.