Systems and methods to respond to error detection
US8572455B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2009 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Aug 29, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1666
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods to respond to error detection are provided. First data may be received at a first memory controller port in response to a read command issued from the first memory controller port. The read command may be issued as a second read command from a second memory controller port after determining that the first data contains a first uncorrectable error. Second data may be received at the second memory controller port in response to the second read command. A repair write command may be issued from the first memory controller port after determining that the second data does not contain any errors. The repair write command may initiate writing the second data from the first memory controller port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.