Method for performing pattern decomposition for a full chip design
US8572521B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2008 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Oct 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/70
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.