Fabricating method of semiconductor element
US8575034B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2011 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Nov 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a fabricating method of a semiconductor element. First, a substrate is provided and a first layout structure having a first width is formed on the substrate. Then, an etching mask is formed to cover the first layout structure, and the etching mask exposes a portion of the first layout structure. After that, the first layout structure is etched with the etching mask to form a second layout structure having a second width. The second width is less than the first width. This fabricating method is capable of finishing the fabrication of gate structures in two different directions. Accordingly, the layout flexibility is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.