Non-planar quantum well device having interfacial layer and method of forming same
US8575653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2010 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Jul 31, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.