Col-based semiconductor package including electrical connections through a single layer leadframe
US8575739B2 · kind B2 · utility
0Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 6, 2011 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Nov 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package is disclosed including a leadframe, memory die and controller die, one or more of which are customized to facilitate electrical connection of the memory and controller die bond pads to the contact pads of the host device via the leadframe. By customizing one or more of the leadframe, memory die and controller die, an interposer layer normally required to connect the die in the semiconductor package with a host device may be omitted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.