Method of testing data retention of a non-volatile memory cell having a floating gate
US8576648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2011 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Jan 23, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of decreasing the test time to determine data retention (e.g. leakage current) of a memory cell having a floating gate for the storage of charges thereon. The memory cell is characterized by the leakage current having a rate of leakage which is dependent upon the absolute value of the voltage of the floating gate. The memory cell is further characterized by a first erase voltage and a first programming voltage, applied during normal operation, and a first read current detected during normal operation. The method applies a voltage greater than the first erase voltage or greater than the first programming voltage, to over erase the floating gate. The memory cell including the floating gate is subject to a single high temperature bake. The memory cell is then tested for data retention of the floating gate based on the single high temperature bake.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.