Power managed lock optimization
US8578079B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2012 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Nov 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/526
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.