Hierarchical memory architecture using a concentrator device
US8578095B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2009 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Feb 2, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hierarchical memory storage using a concentrator device that is located between a processor and memory devices. The concentrator device includes a page buffer, a Phase-Change Memory (PCM) memory array, and a configurable Error-Correcting Code (ECC) engine to accommodate temporary storage for data transfers between the processor and the memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.