Infrastructure support for accelerated processing device memory paging without operating system integration
US8578129B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 14, 2011 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | May 29, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a CPU, the CPU having multiple CPU cores, each core having a first machine specific register, a second machine specific register, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.