Loop predictor and method for instruction fetching using a loop predictor
US8578141B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 16, 2010 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Feb 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/381
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A loop predictor and a method for instruction fetching using a loop predictor. A processor may include a loop predictor in addition to a primary branch predictor. A relatively common scenario in program execution is that a set of branches repeat over and over forming a loop. The loop may be detected based on a repeated pattern of access to a data structure used for branch prediction. Once a loop is detected and it may be determined whether the codes would stay in the loop for at least a duration sufficient to disable the branch prediction. On a determination that the detected loop is locked, a sequence of instruction addresses in one iteration of the detected loop may be captured in a buffer and the branch predictor may be turned off and a sequence of fetch instructions may be played from the buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.