Chip assembly

US8580612B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Horst Theuss · Wenzenbach, DE
• Georg Meyer-Berg · Birkenfeld, DE

Key dates

• Filing date: Feb 12, 2009
• Grant date: Nov 12, 2013
• Expiry date: Jul 17, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/181
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of manufacturing an array of semiconductor devices comprises providing a first carrier having multiple chip alignment regions. Multiple chips are placed over the multiple chip alignment regions. Then, alignment of the chips to the multiple chip alignment regions is obtained. The multiple chips are then placed on a second carrier. The first carrier is detached from the multiple chips. An encapsulation material is applied to the multiple chips to form an encapsulated array of semiconductor chips. The second carrier is then detached from the encapsulated array of semiconductor devices.