Semiconductor stacks including catalytic layers
US8581319B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2013 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Jan 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2−x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.