Silicon based microchannel cooling and electrical package
US8581392B2 · kind B2 · utility
7Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2012 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Dec 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip stack; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chip stacks. The chip package further includes a cooling lid disposed above the chip stack providing additional cooling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.