Fast programming memory device
US8582364B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2011 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Nov 10, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.