Error detection in FIFO queues using signature bits
US8583971B2 · kind B2 · utility
1Cited by
7References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2010 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Jan 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first in, first out (FIFO) queue includes logic to provide detection of operational errors in the FIFO queue. The FIFO queue includes entries to store data written to the FIFO queue and signature bits, each signature bit corresponding to one of the entries. A test pattern and a read signature register includes a number of bits greater than a depth of the FIFO queue. A comparator compares the test pattern to the read signature register and output an error signal indicating whether the test pattern matches the read signature register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.