Assertion-based design partitioning
US8584063B1 · kind B1 · utility
1Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2012 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Sep 7, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach is provided in which a computing system retrieves a design description that corresponds to an electronic circuit design. The computing system selects an assertion corresponding to the electronic circuit design, which includes one or more assertion signal identifiers corresponding to one or more description signal points included in the design description. Next, the computing system creates a partitioned region from the design description based upon the description signal points. The computing system compiles and verifies the partitioned region that, in turn, verifies the electronic circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.