Methods for fabricating sub-resolution alignment marks on semiconductor structures
US8585915B2 · kind B2 · utility
4Cited by
10References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2007 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Dec 28, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24322
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one sub-resolution alignment mark extending partially into the dielectric material. At least one opening is formed in the dielectric material. Semiconductor structures comprising the sub-resolution alignment marks are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.