Power semiconductor arrangement and method for producing a power semiconductor arrangement

US8586420B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thilo Stolze · Arnsberg, DE
• Guido Strotmann · Uchte, DE
• Karsten Guth · Soest, DE

Key dates

• Filing date: Sep 29, 2011
• Grant date: Nov 19, 2013
• Expiry date: Mar 14, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/13091
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.