Interconnection structure for N/P metal gates
US8586428B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2012 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Sep 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This description relates to a method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS). The method includes forming a first opening in a dielectric layer over a substrate and partially filling the first opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the first opening. The method further includes forming a second opening adjoining the first opening in the dielectric layer over the substrate and depositing a first work-function metal layer in the first and second openings, whereby the first work-function metal layer is over the second work-function metal layer in the first opening. The method further includes depositing a signal metal layer over the first work-function metal layer in the first and second openings and planarizing the signal metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.