Methods for fabricating integrated circuits with ruthenium-lined copper
US8586473B1 · kind B1 · utility
36Cited by
1References
20Claims
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Key dates
| Filing date | Jun 26, 2012 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Jun 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a dielectric layer defining a plane. In the method, the dielectric layer is etched to form trenches. Then, a ruthenium-containing liner layer is deposited overlying the dielectric layer. The trenches are filled with copper-containing metal. The method includes recessing the copper-containing metal in each trench to form a space between the copper-containing metal and the plane. The space is filled with a capping layer. The layers are then planarized to at least the plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.