Patent · US Active

Memory system with redundant data storage and error correction

US8589737B2 · kind B2 · utility

8Cited by

9References

20Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Michael Rohleder · Unterschleißheim, DE
Gary Hay · Whinstanes, AU
Stephan Mueller · Durham, US
Manfred Thanner · Neubiberg, DE

Key dates

Filing date	Jun 20, 2008
Grant date	Nov 19, 2013
Priority date	—
Expiry date	Jan 25, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/0411
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system comprises at least two random access memory (RAM) elements arranged to store data redundantly. The system further comprises RAM routing logic comprising comparison logic operably coupled to the at least two RAM elements and arranged to compare redundant data read from the at least two RAM elements, and check and validation logic, independent of the RAM routing logic, operably coupled to the at least two RAM elements and arranged to additionally detect an error in the redundant data read from the at least two RAM elements and provide an error indication signal to the RAM routing logic in response thereto. The RAM routing logic further comprises selection logic arranged to dynamically select redundant data from one of the at least two RAM elements based on the comparison of the redundant data and the error indication signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.