Method for packaging an electronic device assembly having a capped device interconnect
US8592241B2 · kind B2 · utility
12Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2011 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Jan 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a thin package that encapsulates a capped MEMS device electrically coupled with one or more encapsulated semiconductor devices is provided. A wafer-level packaging methodology is used in which the capped MEMS device is electrically coupled to a package interconnect, which then allows for electrical coupling to the one or more encapsulated semiconductor devices, as well as external connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.