Erasable programmable single-ploy nonvolatile memory
US8592886B2 · kind B2 · utility
50Cited by
6References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 13, 2012 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Aug 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.