Structure and method for forming conductive path in resistive random-access memory device
US8593854B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2012 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | May 22, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array and forming method for resistive-RAM (RRAM) devices provides for the simultaneous selection of multiple bit cells and the simultaneous forming of the RRAM resistive elements within the selected bit cells. The bit cells each include a resistive element and a transistor and are arranged vertically along vertical bit lines. The resistive elements of the bit cells are coupled to source lines that are parallel to word lines and perpendicular to the vertical bit lines. The bit lines are maintained at different biases. A high voltage is applied to one of the source lines coupled to adjacent resistive elements of bit cells disposed along more than one vertical bit line. When the associated transistors are turned on by a sufficiently high gate voltage, the desired RRAM resistive elements along one of the bit lines are formed without stressing other bit cells of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.