Patent · US Active

Systems and methods of sectioned bit line memory arrays

US8593860B2 · kind B2 · utility

26Cited by

34References

58Claims

0Family size

Assignee

GSI Technology Inc. · US

Inventors

LeeLean Shu · Los Altos, US
Chenming W. Tung · San Jose, US
Hsin You S. Lee · Campbell, US

Key dates

Filing date	Dec 9, 2011
Grant date	Nov 26, 2013
Priority date	—
Expiry date	Dec 9, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/419
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described. In one illustrative implementation, the sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. In other implementations, an SRAM memory device may be configured involving sectioned bit lines and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.