Semiconductor defect classifying method, semiconductor defect classifying apparatus, and semiconductor defect classifying program
US8595666B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2010 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | May 14, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N21/95607
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.