Local objective optimization in global placement of an integrated circuit design
US8595675B1 · kind B1 · utility
4Cited by
4References
12Claims
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Key dates
| Filing date | Jun 30, 2012 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Jun 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A global placement phase of physical design of an integrated circuit includes iteratively spreading a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules and optimizing module placement by preserving global module density while improving a local objective, such as local wirelength and/or local density, in individual subareas among a plurality of subareas of the die area. After global placement, detailed placement of modules in the plurality of subareas is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.