Self-aligned embedded SiGe structure and method of manufacturing the same
US8598009B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 26, 2012 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | May 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.