Multi-layer circuit assembly and process for preparing the same
US8598467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2011 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Nov 9, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49158
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a multi-layer circuit assembly is provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; (c) removing the dielectric coating in a predetermined pattern to expose sections of the substrate; (d) applying a layer of metal to all surfaces to form metallized vias through and/or to the electrically conductive core; (e) applying a resist to the metal layer to form a photosensitive layer thereon; (f) imaging resist in predetermined locations; (g) developing resist to uncover selected areas of the metal layer; and (h) etching uncovered areas of metal to form an electrical circuit pattern connected by the metallized vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.