Non-volatile FINFET memory array and manufacturing method thereof
US8598646B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2011 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Aug 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.