Barrier structure
US8598676B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2012 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Aug 3, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A starting substrate in the form of a semiconductor wafer (1) has a first side and a second side, the sides being plane-parallel with respect to each other, and has a thickness rendering it suitable for processing without significant risk of being damaged, for the fabrication of combined analogue and digital designs, the wafer including at least two partitions (A1, A2; DIGITAL, ANALOGUE) electrically insulated from each other by insulating material (2; 38; 81; L) extending entirely through the wafer. A method for making such substrates including etching trenches in a wafer, and filling trenches with insulating material is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.