Semiconductor structure formed by double patterning technique
US8598712B2 · kind B2 · utility
3Cited by
5References
6Claims
0Family size
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Key dates
| Filing date | Jun 20, 2011 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Oct 13, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.