Semiconductor device comprising through hole vias having a stress relaxation mechanism

US8598714B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Torsten Huisinga · Dresden, DE
• Michael Grillberger · Radebeul, DE
• Jens Hahn · Dresden, DE

Key dates

• Filing date: Dec 16, 2010
• Grant date: Dec 3, 2013
• Expiry date: Jun 19, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In a semiconductor device, through hole vias or through silicon vias (TSV) may be formed so as to include an efficient stress relaxation mechanism, for instance provided on the basis of a stress relaxation layer, in order to reduce or compensate for stress forces caused by a pronounced change in volume of the conductive fill materials of the through hole vias. In this manner, the high risk of creating cracks and delamination events in conventional semiconductor devices may be significantly reduced.