Patent · US Active

Circuits configured to remain in a non-program state during a power-down event

US8599597B2 · kind B2 · utility

2Cited by
10References
40Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 7, 2012
Grant dateDec 3, 2013
Priority date
Expiry dateJul 6, 2032

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C17/18
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

In a particular embodiment, an apparatus includes a one-time programmable (OTP) memory circuit configured to be responsive to a programming voltage. The OTP memory circuit includes an OTP memory array including OTP memory cells, a first power switch configured to decouple the OTP memory array from the programming voltage, and a second power switch configured to decouple a subset of the OTP memory cells from the programming voltage.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.