Patent · US Active

Interface control for improved switching in RRAM

US8599601B2 · kind B2 · utility

5Cited by
105References
8Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 15, 2013
Grant dateDec 3, 2013
Priority date
Expiry dateFeb 15, 2033

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C2213/33
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.