Full chip wear leveling in memory device
US8601202B1 · kind B1 · utility
43Cited by
6References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 26, 2009 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Mar 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems to wear level a non-volatile memory device across partitions. In an embodiment, a memory device performs background operations to swap host addressable memory partitions with a spare memory partition outside of the host address space. In one embodiment, the background inter-partition wear leveling operations are appended to a user erase operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.