Debugger recovery on exit from low power mode
US8601315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2010 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Nov 20, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device is configured with components to enable debugging of the device's entry into and exit from a low power mode. The device includes: core logic, debug components, and a power management module (PMM). When the device exits a low power mode in which the states of the debug components are lost, the PMM prevents the core logic from resuming processing operations until the debug components have been re-configured to their prior states. The PMM either holds the core logic in reset or alternatively withholds power to the core logic. Reconfiguration of the debug components is initiated by a connected debugger, which can set one or more control and status (CS) register values within the device. The CS register values determine when the PMM prevents the core logic processing from resuming and when the PMM enables core logic processing to resume following the device's return from low power mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.