High productivity combinatorial workflow for post gate etch clean development
US8603837B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2012 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Jul 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.