Multi-stage silicidation process
US8603915B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2011 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Feb 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-stage silicidation process is described wherein a dielectric etch to expose contact regions is timed to be optimal for a highest of the contact regions. After exposing the highest of the contact regions, a silicide is formed on the exposed contact region and the dielectric is re-etched, selective to the formed silicide, to expose another contact region, lower than the highest of the contact regions, without recessing the highest of the contact regions. The process then forms a silicide on the lower contact region. The process may continue to varying depths. Each subsequent etch is performed without the use of additional masking steps. By manipulating diffusive properties of existing silicides and deposited metals, the silicides formed on contact regions with differing depths/height may comprise different compositions and be optimized for different polarity devices such as nFET and pFET devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.